A redistribution layer (RDL) is an important feature in high density chip packaging. Conventional RDLs can relocate integrated circuit bond pads before flip chip bumping, for example, offering a feasible and low cost method to distribute power and grounding contacts. RDLs also redistribute wafer-level chip-scale packages to ball-grid arrays for external connection. Moreover, 3D packaging and system-in-package modules often depend heavily on redistributed bond pads.
Conventional RDL processes have their drawbacks. Laying down RDL conductors is relatively expensive and time consuming as several metals are deposited in a sequence of thin layers over a passivation layer on the wafer surface. Multiple metals are required to provide adhesion, barrier strength, electrical conduction, and protection. Layers of various metals including but not limited to copper, aluminum, gold, titanium, nickel, etc., may be deposited as conductive trace lines for relocating the bond pads. The deposited metals form a conduction pattern that may vary in thickness at different locations. These variations in thickness can cause high frequency signal transmission loss. Moreover, in the case of fan-out wafer level packaging (FOWLP), conventional RDL overlies the transition of fan-in and fan-out boundary areas, where there is large interface stress caused by mismatched coefficients of thermal expansion (CTE) of silicon and encapsulation mold compound.